< (less than)    halve the clock speed (if > 1 MHz)
> (greater than) double the clock speed (if < 8 MHz)
= (equal sign)   display the clock speed in Register R24 (if '}' is enabled)

At least 2.4 Volts are needed for reliable operation at 8 MHz, extrapolated from the ATmega specifications. Using a slower, on-command speed reduction capability facilitates changing the system clock to 4 MHz, for example, so a Vcc of down to 1.8 can still provide reliable operation. This can also be useful for power reduction during sleep cycles or simply low-power applications or those where power drops may occur but the ability to operate, even slowly, is still required.

Since these commands are issued from the command line, some characters may be in the Serial transmit buffer at that time. If so, at some will very likely be garbled until the two UBRR Registers are updated to reflect the comm rate configured in EEwCOM1_xBPS, noting that that varaiable is the desired comm rate divided by 10. The UBRR update happens immediately after the CPU speed change.

Computing devices implement serial communication clocking in quite a variety of ways. For successful asynchronous communication to occur, two devices must have the same data format: number of start bits, data bits, stop bits, and parity selection. They must also be "clocked" at a compatible rate. Clocks are generated by hardware, perhaps an older ACE (Asynchronous Communication Element) and ART (Asynchronous Receiver Transmitter), or the newer UART (Universal Asynchronous Received Transmitter) USART (Universal Synchronous/Asynchronous Received Transmitter.) The ATmega 328P has a single USART built-in. The new 328PB has two.

Due, in part, to the differences between devices and how they derive their clock signals, despite being configured for the same communication rate, there is often some bit rate inequality. These difficulties become apparent when changing baud rate divisors (i.e., the two UBRR registers.)

If you have trouble, try configuring the ATmega 328 comm rate at a little slower speed than standard BPS rates, or the computer at a little faster rate than standard. For example, we often run the computers at about 59,000 BPS while the 328P is configured for 57,600 BPS. The Windows-based terminal software which SSG designed and uses can be configured for any BPS rate, not just the common "evenly divisible by 300" BPS rates. When using 59,000 to 60,000 BPS, communication was checked and successfully maintained when switching from 8 MHz, to 4 MHz, to 2 MHz, to 1 MHz, to 2 MHz, to 4 MHz, and finally back to 8 MHz.

Another less attractive option is to slow both comm rates down to something like 9,600 BPS. The divisor differences are not so noticeable at slower speeds.

In any case, other system clock values are validated once each second, regardless of any system clock change. If you monitor the heartbeat LED, for example, you may see if stutter (for less than 2 seconds if decreasing the system clock speed or for less than 1/2 second if increasing it) until bMILLIS_INC, the millisecond increment and bFRACT_INC, the fractional time remnant compensation adder, are recalculated. That recalcuation occurs once at the start of each "new" second and is based on the CLKPR value then.

There are no System Commands provided to increase, decrease, or check speed, other than through the Command Processor or a script. A command to increase speed when already running at 8 MHz is ignored, as is one to decrease below 1 MHz.