Z[+|-|W| [&|^||]=[ ]###]
  where [ ] means zero or more spaces,
  '+'   sets   the BIT_SLEEP_ENABLE bit in bFlags_Sleep,
  '-'   clears the BIT_SLEEP_ENABLE bit in bFlags_Sleep,
  'W'   writes the present value of bFlags_Sleep variable to EEbFlags_Sleep,
  "&="  is the BITWISE AND assignment operator,
  "^="  is the BITWISE XOR assignment operator,
  "|="  is the BITWISE OR  assignment operator,
  '='   is the EQUAL assignment operator,
  "###" is a numeric value, 0 to 0xFF, used to modify the bFlags_Sleep operand

Notes:
  No distinction is made between uppercase and lowercase.
  "Z" alone (not even a space after it) toggles BIT_SLEEP_ENABLE in bFlags_Sleep
  bFlags_Sleep is only read from EEbFlags_Sleep during bootup and is not reread.
  bFlags_Sleep can be written using the "ZW" command.

Sleep mode is designed for power conservation. If there is no need to conserve power, then there is little or no need to use Sleep mode. When running on battery, or solar power with supercaps, for example, Sleep mode can really help the MCU conserve its power resources.

First, here are the EEPROM variables used by the sleep routines:

Name		EEPROM Address	Default Value	Description
EEbFlags_Power		2	0	Power control bits for bFlags_Power in SRAM, which are:
	BIT_PWR_USE_PRR	0 (B00000001 = 1)	0	Enable (= 1) or disable (= 0) use of EEbPRR_Disable and EEbPRR_Enable
	BIT_PWR_AUTOSLOW	1 (B00000010 = 2)	0	(only used by the 1284P and higher version of MIRTOS)
	BIT_PWR_AUTOFAST	2 (B00000100 = 4)	0	(only used by the 1284P and higher version of MIRTOS)
	BIT_PWR_CONSERVE	3 (B00001000 = 8)	0	Use bits BIT_PWR_CLKPR_LOW and BIT_PWR_CLKPR_HIGH below
	BIT_PWR__spare4__	4 (B00010000 = 16)	0	(unused, spare, reserved)
	BIT_PWR_WS2812_OFF	5 (B00100000 = 32)	0	Send the OFF command to the first 8 WS2812 GRB LEDs
	BIT_PWR_CLKPR_LOW	6 (B01000000 = 64)	0 -->	Two (2) bits which change the CLKPR divisor during sleep:     B00 = divide by 1, B01 = divide by 2, B10 = by 4, B11 = by 8
	BIT_PWR_CLKPR_HIGH	7 (B10000000 = 128)	0 -->
EEbFlags_Sleep		6	0x84 = B10000100	Sleep mode control bits for bFlags_Sleep in SRAM, which are:
	BIT_SLEEP_ENABLE	0 (B00000001 = 1)	0	Enable (= 1) or disable (= 0) the device sleep feature
	BIT_SLEEP_WDFAST	1 (B00000010 = 2)	0	EEbTime_IRQAwake timer units: 100 mSec (slow = 0) or 1 mSec (fast = 1)
	BIT_SLEEP_DOS	2 (B00000100 = 4)	1	Leave DOs alone (= 0) or turn DOs off (= 1) during sleep time
	BIT_SLEEP_NRF_LOW	3 (B00001000 = 8)	0	Bit for Register EICRA bit ICS00
	BIT_SLEEP_NRF_HI	4 (B00010000 = 16)	0	Bit for Register EICRA bit ICS01
	BIT_SLEEP_TIME_L	5 (B00100000 = 32)	0 -->	Three (3) bits which set Watchdog Timer sleep time, in Seconds:     B000 = 0.064, B001 = 0.128, B010 = 0.256, B011 = 0.512,     B100 = 1.024, B101 = 2.048, B110 = 4.096, B111 = 8.192
	BIT_SLEEP_TIME_M	6 (B01000000 = 64)	0 -->
	BIT_SLEEP_TIME_H	7 (B10000000 = 128)	1 -->
EEbTime_IRQAwake		33 = 0x21	40 = 0x28	Time awake after IRQ (except WDT), in 0.1 secs (40 = 4.0 sec)
EEbTime_BlinkOn		34 = 0x22	5	Minimum time awake after WDT (WatchDog Timeout), in mSec
EEbPRR_Disable		35 = 0x23	0x00 = B00000000	Peripherals which PRR disables (if EEbFlags_Power.BIT_PWR_USE_PRR)
	BIT_PRR_ADC	0 (B00000001 = 1)	0	Shut down the Analog to Digital Conversion module during sleep
	BIT_PRR_USART0	1 (B00000010 = 2)	0	Shut down the USART0 module during sleep
	BIT_PRR_SPI	2 (B00000100 = 4)	0	Shut down the Serial Peripheral Interface module during sleep
	BIT_PRR_TIM1	3 (B00001000 = 8)	0	Shut down the Timer/Counter1 module during sleep
	BIT_PRR__spare4__	4 (B00010000 = 16)	0	(unused, spare, reserved)
	BIT_PRR_TIM0	5 (B00100000 = 32)	0	Shut down the Timer/Counter0 module during sleep
	BIT_PRR_TIM2	6 (B01000000 = 64)	0	Shut down the Timer/Counter2 module during sleep
	BIT_PRR_TWI	7 (B10000000 = 128)	0	Shut down the Two-Wire Interface module during sleep
EEbPRR_Enable		36 = 0x24	0xFF	Peripherals which PRR reenables (if EEbFlags_Power.BIT_PWR_USE_PRR)
	This variable uses the same bit definitions as EEbPRR_Disable above; both are used for the MCU Register PRR (at SRAM address 0x64)
EEbSMCR_Bits		37 = 0x25	0xFF	Value to write to SMCR (0x05 used if 0xFF or LSBit is set)
EEbWDT_Count		38 = 0x26	42 = 0x2A	Watchdog Timeout count before briefly waking up

After verifying, or setting, all of the default values shown in the table above, invoke Sleep mode by issuing the 'Z' command. Recall that 'Z' alone (i.e., with no other characters on the command line) toggles Sleep mode. That command flips a single bit. In this configuration, if the dedicated Discrete Alarm Input (the A328 pin D3) changes, either from logic 1 to logic 0, or vice versa, INT1 causes Sleep mode to be suspended for the preset time.

The underlined values in EEPROM below are those of interest for a 328P from the table above:
   EEbFlags_Power at address 2 is 0, so BIT_PWR_USE_PRR is disabled,
   EEbFlags_Sleep at address 6 is 0x84, so sleep is disabled, turn DOs off, use 1.024 WDT, and
   EEbTime_IRQAwake at address 0x21 (= 33) is 0x28 (= 40), selecting a 4.0 second delay.

>DES
EEPROM contents:
0000:  10 21 00 9F 01 01 84 FF-04 00 FF FF 28 3C 50 FF  .!..........(.P.
0010:  C0 00 3F FF 40 08 03 67-FF 25 74 FF FF FF FF FF  ..?.@..g.%t.....
0020:  24 28 05 00 FF FF 2A FF-FF 14 30 20 00 40 FF FF  $(...*....0 .@..
0030:  80 16 FF FF FF FF FF FF-60 00 B0 00 90 01 FF FF  ........`.......
0040:  FF FF FF FF FF FF 00 AF-FF FF FF FF FF FF FF FF  ................
>                                                                               

Three of the variables in EEPROM above correspond to the underlined values in SRAM below:
   bFlags_Power at SRAM address 0x126 reads its value from EEbFlags_Power,
   bFlags_Sleep at SRAM address 0x128 reads its value from EEbFlags_Sleep, and
   Register R6 reads its value from EEbTime_IRQAwake once each second.

>DS+ 0x126 3   ; bFlags_Power (at 0x126) and bFlags_Sleep (at 0x128):
SRAM contents:
0120:                    00 00-84                             ...
>DS+ 5 2
SRAM contents:
0000:                 09 28                                  .(
>R             ; SRAM address 6 and Register R6 are the same location

 10   32   54   76   98  1110 1312 1514 1716 1918 2120 2322 2524 2726 2928 3130
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
0000 05C4 097C FF28-0004 0000 0000 4000-0001 007E 5201 0000-0000 0230 0280 3166
>                                                                               

When either 1) BIT_SLEEP_ENABLE is OFF, or 2) EEbTime_IRQAwake in R6 is zero, or 3) the Unit Serial Number at FLASH Address 0x00E0 is invalid, Sleep mode is disabled. The Operating System continuously refreshes the wStartTmAwake sleep timer's starting time to the present time whenever Sleep mode is disabled. Once all three of the conditions are met, it stops resetting the starting time, which allows the Sleep Timer to run. Once the EEbTime_IRQAwake time has passed, the timer times out and the device enters Sleep mode.

To toggle Sleep mode ON, enter 'Z'. After the delay, a WS2812 command to extinguish the Outputs may be called, the six (6) Discrete Outputs themselves turned off, the EEbSMCR_Bits variable read, validated and set, interrupts enabled and the device enters Sleep mode. If an Alarm Input (PIND3) changes state, an IRQ1 occurs. IRQ1 is always enabled to exit Sleep mode. The nRF Radio Interrupt is IREQ0 and must be enabled (using BIT_NRF_ENABLE_IRQ) for IRQ0 to occur. If either IRQ0 or IRQ1 occurs during Sleep mode, the device exits Sleep mode for the EEbTime_IRQAwake time. If 'Z' is entered any time the device is awake, it toggles Sleep mode.

The WatchDog Timer is also used to awaken the device from Sleep mode. The WatchDog Timer interval for Run and the Sleep modes need not be the same value (the default WDTCSR = 0x29.) The device will remain asleep until the WatchDog Timer wakes it up unless an IRQ0 or IRQ1 occurs. The Operating System will decrement the loop counter (preset to EEbWDT_Count) until it reaches zero, at which time it will exit Sleep mode just as if an IRQ0 or IRQ1 occurred, with one exception. The Operating System saves the reason why Sleep mode was ended and will set the sleep reentry timer to EEbTime_BlinkOn instead of EEbTime_IRQAwake. This produces a very short window (i.e., less than 250 mSec.) to toggle Sleep mode off. It is intended that this be like a smoke alarm blip - very brief.

The total amount of time between these short blip, when no IRQ0 or IRQ1 has occurred is the time selected by the high three (3) bits of EEbFlags_Sleep (0.064 to 8.192 Seconds) times the EEbWDT_Count value (1 to 256), so the time between "blips" would range from 0.064 to 2,097.152 Seconds (about 35 minutes.)

>Z
>    ; After it is awakened, try changing EEbTime_IRQAwake:
>E 33 += 10
>