Microcontroller overview

It would be very presumptious if we were to try to explain how the Atmel® ATmega family of microcontrollers work on a single webpage, particularly since the manufacturer has devoted thousands of .PDF pages to doing precisely that. At the bottom of this page are some suggested web resources to obtain and make a part of your reference library.

Fortunately, we don't need to know everything about the ATmega family of microcontrollers to get started. We do need to have an idea of what hardware resources are available in each, however. Those hardware resources have specific purposes and are called by various names, which are:

FLASH Memory from which ALL program instructions are executed and into which program instructions and other data, including character strings and constants, may be written. This memory is preserved through power cycles, but can also be changed programatically. The Atmel documentation indicates that the FLASH BYTEs have a life of least 10,000 write/erase cycles.
EEPROM Electrically Erasable Programmable Read Only Memory Memory locations used for semi-permanent data storage which are also preserved through a power cycle. It is more easily changed than FLASH, but not as easily as RAM. The Atmel documentation says that they can be written and erased at least 100,000 times before they no longer hold their value.
RAM or SRAM Static Random Access Memory Memory locations used for temporary data storage, which are not retained during a power cycle. It is this memory which holds the serial port buffers, and any other temporary data values. It has no documented read/write/erase cycle limit.
Registers These are locations with special purposes, such as input ports, output ports, harware configuration BYTEs, timers, counters, device or subsystem status flags, or the stack pointer. They are located at the beginning of the SRAM address space. There are 256 (0 to 0xFF) reserved Register addresses in the 328P and 1284P, while the 2560 has 512 (0 to 0x1FF) reserved Registers. Most can be read or written using the same instructions as SRAM. There are a few sensitive Registers which require special handling, such as being written within a specific short time after a particular bit is toggled in order to prevent unintentional changes. There are thirty-two (32) special data storage and operational Registers, named R0, R1, R2, ... to R31 (called "R## Registers" below), which can be saved to and restored from the Stack. The R## Registers occupy the first thirty-two (32) SRAM addresses. All arithmetic, comparison, data transfer, bit shifting, and numeric operations are performed using one or more R## Registers.
Stack These are locations in the highest SRAM address space which are used as LIFO Last In, First Out storage to temporarily save an R## Register value or FLASH address. An R## Register value is saved whenever a PUSH instruction with a specific R## Register is encountered in the program flow. A saved value is placed into a specific R## Register whenever a POP instruction is executed. A FLASH address is saved whenever a CALL or RCALL instruction is encountered in the program flow or an Interrupt occurs. A FLASH address is loaded into the Instruction Pointer (or "Program Counter") when a RETURN or RETI RETurn from Interrupt instruction is encountered in program flow. The stack can also also used for very temporary memory storage by a subroutine.

The ATmega MCU family uses Harvard architecture, which means that program instructions and data storage use physically separate locations. This also means that program instructions can be written to FLASH and have the same permanent physical address each time that power is cycled to the device. This computer architecture is in contrast to that used by our Personal Computers. They use von Neumann architecture, in which both program instructions and data are loaded into SRAM, usually from a Permanent Disk Drive. Program instructions are then executed out of SRAM.

There are some commands built into MIRTOS which display the contents of the R## Registers at specific times. One version can be invoked from the command line. The other two (2) are system routines, which may be embedded into the flow of your program and executed as they are encountered. These system routines are named DumpRegisters and DumpRegs_Begin. They will be explained more thoroughly in moment.

From the COM1 console command line, the commands syntax is either "R" or "R+". The second version also dumps the Stack after the Registers. The configuration BYTE bDumpRegFlags is used by all of the Register Dump routines. It is located at SRAM address 0x1DF in the 328P or 1248P, or 0x2DF in the 2560. Note that in the example below, the terminal width only needs to be the usual 80 characters for the first example, but when displaying the Stack Pointer, Return Address and Status Register (or FLAGs BYTE), the terminal width should be changed to 101 characters.

>ES 0x1DF = 4      ; Only dump the Registers
>R

 10   32   54   76   98  1110 1312 1514 1716 1918 2120 2322 2524 2726 2928 3130
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
0000 0B50 0911 FF28-0004 0000 0000 6000-0001 007F 5201 0000-0000 0230 0280 3158
>ES 0x1DF = 0x3F   ; Include the Stack Poiner, Return Address, and FLAGs
>r                 ; Accept either uppercase or lowercase

 10   32   54   76   98  1110 1312 1514 1716 1918 2120 2322 2524 2726 2928 3130  SP  RetAdd   SREG
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ------ --------
0000 0285 091B FF28-0004 0000 0000 6000-0021 007F 5201 0000-0000 0230 0280 3158 08F5  69DE  Ithsvnzc
>r+                ; Also dump the stack after the Registers

 10   32   54   76   98  1110 1312 1514 1716 1918 2120 2322 2524 2726 2928 3130  SP  RetAdd   SREG
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ------ --------
0000 02CB 091F FF28-0004 0000 0000 6000-0021 007F 5202 002B-002B 0230 0280 3158 08F5  69DE  Ithsvnzc
STACK contents:
08F0:                 31 34 EF-31 29 30 02 30 FF 3A D6       14.1)0.0.:.

>ES 0x1DF |= 64    ; Set BIT_DT_DUMP_STACK to always dump the stack
>R                 ; Now just R alone dumps the stack as well

 10   32   54   76   98  1110 1312 1514 1716 1918 2120 2322 2524 2726 2928 3130  SP  RetAdd   SREG
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ------ --------
0000 02D2 091F FF28-0004 0000 0000 6000-0021 007F 5202 002B-002B 0230 0280 3158 08F5  69DE  Ithsvnzc
STACK contents:
08F0:                 31 34 EF-31 29 30 02 30 FF 3A D6       14.1)0.0.:.

>

The Registers are shown in pairs for a couple reasons. The first is that they are often used and copied in WORD pairs. In fact, the MOVWCopy a Register pair AVR instruction copies one Register pair into another in a single clock cycle. For example, the MOVW R26, R24 instruction copies R24 to R26 and R25 to R27. Register pairs, like those above are often shown as R25:R24 and R27:R26 throughout this documentation. Another reason to show them in pairs was to make the ASCII representation of all 32 Register values (64 BYTEs) fit on one row of text, with a space between pairs, and still have the Register values be easy to read.

When registers are used as a pair, they are treated as a 16-bit value, which is 0 to 0xFFFF hexadecimal, or 0 to 65,535 decimal. The odd-numbered register of the pair holds the High-Order portion and the even-numbered register holds the Low-Order portion. You may see them called "most significant BYTE" (MSB or LSByte) and "least significant BYTE" (LSB or LSByte) in this documentation. If R27:R26 in the example above were added to R25:R24, the value in R25:R24 would be 0x025B, and the value in R27:R26 would be unchanged.

The register pair R27:R26 is also called the 'X' pointer, used to specify a 16-bit address. Similarly, R29:R28 is the 'Y' pointer and R31:R30 the 'Z' pointer. A pointers, they are used to read a BYTE from SRAM into a Register, called "Load Indirect from Data Space" in AVR documentation or to write a BYTE from a Register back to SRAM. In following that convention, SPH:SPL (or just SP in the Register dump row) is a reference to the Stack Pointer. Its two 8-BIT Registers, SPH and SPL, comprise the 16-BIT WORD, which can reference any SRAM address.

The RetAdd column in the Register dump row is the Return Address that is on the Stack. This is the instruction AFTER the one which called the Register Dump routine. It helps to know this when you've placed several calls in your code block or when you used DumpRegs_Begin.

The SREG column in the Register dump row contains the group of eight (8) FLAG bits in Register SREG. Uppercase letters signify that the FLAG is TRUE or logic 1, while lowercase signify the FLAG is FALSE, or logic 0. So "Ithsvnzc" means that global Interrupts are enabled, the 'T' flag is OFF, as are all the other FLAGS: Half-carry, Sign, two's complement oVerflow, Negative, Zero, and Carry.

As mentioned above, both of the system calls to DumpRegisters or DumpRegs_Begin cause the Register and possibly the Stack to be displayed out the COM1 serial port. The only difference between the two routines is that DumpRegisters can be toggled on and off using the '}' firstkey, while DumpRegs_Begin skips past checking that and always performs the Register dump. Sometimes more than a dozen Register Dumps can occur in one second, so the Return Address is crucial in identifying which caused the output. The DumpStack system call is available and can be called by itself, if desired. In practice, that output tends to be more confusing without the context of the Registers.

All Register Dump and Stack Dump routines preserve the Registers and SREG (FLAGs) BYTE, so making either one of those calls does not change the Microcontroller's working environment.

See also:
    More detailed information about the "R" command

Some additional documentation, hardware resources, and Microcontroller information:

MCU Local file Google DigiKey Mouser SparkFun FLASH EEPROM Registers SRAM
ATmega328P ATmega328P.PDF Search Catalog Catalog Catalog 32 KB = 32,768 = 0x8000 1 KB = 1,024 = 0x400 256 = 0x100 2 KB = 2,048 = 0x800
ATmega1284P   ATmega1284P.PDF Search Catalog Catalog - 128 KB = 131,072 = 0x20000 4 KB = 4,096 = 0x1000 256 = 0x100 16 KB = 16,384 = 0x4000
ATmega2560 ATmega2560.PDF Search Catalog Catalog Catalog 256 KB = 262,144 = 0x40000 4 KB = 4,096 = 0x1000 512 = 0x200 8 KB = 8,192 = 0x2000
Instruction set AVR_InstructionSet.PDF